Flash memory was originally developed as a derivative of Erasable Programmable Read Only Memory (EPROM). Conventional EPROM technology uses hot electron injection (also called avalanche injection) to program the memory and ultraviolet (UV) light to erase the contents of the memory. Avalanche injection of electrons into the floating gate is achieved by applying high positive voltage to both the drain and the control gate, and grounding the source. Exposing the cell to UV light increases the energy of the floating gate electrons to a level where they may jump the energy barrier between the floating gate and the oxide.
Conventional single-transistor cell flash memory technology is similar to single-transistor cell EPROM technology. However, flash memory allows for electrical erasure of the contents of the memory, either of the entire memory array at once or of a sector of the memory at once, by way of cold electron tunneling (also called Fowler-Nordheim tunneling).
An example of a conventional single-transistor cell for flash memory is illustrated in FIG. 1. Such a flash memory cell typically has thinner oxide under the floating gate (between the floating gate (106) and the channel) than an EPROM cell has. The thinner oxide allows for erasure to be achieved via cold electron tunneling between the floating gate (106) and the source (104).
Like programming of EPROM, programming of conventional single-transistor cell flash memory is typically performed by applying high positive voltage to both the drain (102) via the bitline and the control gate (108) via the wordline, while grounding the source (104). This causes hot electron injection from the substrate (101) near the drain (102) to the floating gate (106). This programming by way of hot electron injection is crude in that the charge stored in the floating gate (106) is difficult to control precisely. This inability to control precisely the charge stored in the floating gate (106) is a first disadvantage of conventional single-transistor cell flash memory. This disadvantage makes it difficult to store multi-levels (i.e. more than one bit of information) in a flash cell.
Erasure of conventional single-transistor cell flash memory may be performed by applying a high positive voltage (for example, plus 12 volts) to the substrate (101)and grounding the control gates (108) in a sector. This causes the tunneling of the electrons from the floating gates (106) to the sources (104). Portions of the memory smaller than a sector cannot be erased because the common substrate is shared by all cells in a sector. The size of a sector may be, for example, 512 kilobits of cells for a 4 megabit flash memory organized into 8 sectors. Thus, the inability to erase portions of the memory smaller than a sector is a second disadvantage of conventional single-transistor cell flash memory.
As an alternative to using single-transistor cells, conventional flash memory may instead utilize cells with two or more transistors. For example, each cell may include two transistors: one being a select transistor; and the other being a storage transistor. Utilizing such multiple-transistor cells, erasure of portions as small as a single word have been achieved. However, such multiple-transistor cells are substantially larger than single-transistor cells, and hence are not suitable for high density flash memory applications.
Cell size in conventional flash memory is limited by cell punchthrough requirements. Cell punchthrough occurs when the depletion region of the drain junction merges with the depletion region of the source junction. In order to prevent cell punchthrough, a minimum distance is typically required between drain (102) and source (104) along a bitline (or column). The higher the maximum voltage applied to a drain during operation, the larger the minimum distance must be. In this way, cell punchthrough limits the size of cells along the columnar direction, and so is a third disadvantage of conventional single-transistor cell flash memory.
The present invention relates to flash memory technology which overcomes the disadvantages and problems discussed above. Instead of using a common substrate (101) for each sector, the present invention uses trenches to isolate columnar active substrate regions (304) of the substrate (101) and further provides circuitry for independent access to each of these columnar regions (304).
As a first advantage, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the charge on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Since each bitline may be accessed individually during erase, as well as during programming, a capability is provided to correct for any xe2x80x9covershootxe2x80x9d during the programming of a bit. Programming algorithms may use this capability in order to achieve the storage of more precise voltage levels which is needed for multi-level storage. In addition, additional precision in the control of the stored voltage levels is provided by the present invention because both programming and erase utilize a tunneling mechanism, instead of an injection mechanism.
As a second advantage, the independent access to each of these columnar regions (304) provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Without columnar substrate isolation, all cells would be erased (or at least the charge on the floating gates would be substantially disturbed) by way of the common substrate even if the sources of individual rows were disconnected (or decoded). With columnar substrate isolation, as few as one or two wordlines (also called rows) may be erased at one time by applying a high negative voltage to control gates (108) of the selected wordline, a small positive voltage to the control gates (108) of the unselected wordlines, and a high positive voltage to the active substrate regions (304), while allowing the sources (104) and drains (102) to float. In this case, the n-polarity source line (504) corresponding to the selected wordline (108) floats to a level near to the positive voltage of the active substrate regions (304). Hence, if each wordline has its own source line (504), then one wordline at a time may be so erased. Alternatively, if two neighboring wordlines share a common source line (504), then two neighboring wordlines at a time may be so erased. Moreover, even smaller than one or two word lines, a single cell may be erased by applying a high negative voltage to the control gates (108) in a selected wordline, a small positive voltage to unselected wordlines to serve as an inhibit voltage, grounding the columnar active substrate region (304) corresponding to a particular bitline, and allowing the drains (102) and sources (104) to float. In this case, no voltage is induced in the floating source line (504) because ground does not induce any potential in the floating terminal. Hence, a single cell may be erased.
As a third advantage, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104). This is advantageous in that the minimum distance required by cell punchthrough is reduced. As a result, the size of the cell may be reduced along the columnar direction. Hence, higher densities of flash memory may be achieved.